
2011 Microchip Technology Inc.
DS39932D-page 59
PIC18F46J11 FAMILY
REGISTER 4-3:
DSGPR0: DEEP SLEEP PERSISTENT GENERAL PURPOSE REGISTER 0
(BANKED F4Eh)
R/W-xxxx(1)
Deep Sleep Persistent General Purpose bits
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-0
Deep Sleep Persistent General Purpose bits
Contents are retained even in Deep Sleep mode.
Note 1:
All register bits are maintained unless: VDDCORE drops below the normal BOR threshold outside of Deep
Sleep, or the device is in Deep Sleep and the dedicated DSBOR is enabled and VDD drops below the
DSBOR threshold, or DSBOR is enabled or disabled, but VDD is hard cycled to near VSS.
REGISTER 4-4:
DSGPR1: DEEP SLEEP PERSISTENT GENERAL PURPOSE REGISTER 1
(BANKED F4Fh)
R/W-xxxx(1)
Deep Sleep Persistent General Purpose bits
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-0
Deep Sleep Persistent General Purpose bits
Contents are retained even in Deep Sleep mode.
Note 1:
All register bits are maintained unless: VDDCORE drops below the normal BOR threshold outside of Deep
Sleep, or, the device is in Deep Sleep and the dedicated DSBOR is enabled and VDD drops below the
DSBOR threshold, or DSBOR is enabled or disabled, but VDD is hard cycled to near VSS.